The electromagnetic noises radiated from various electronic devices have been causing serious problems interfering the operation of electronic devices where the information processes are performed at higher speed and lower voltage.
As an effective means reducing the undesirable electromagnetic radiation, a method incorporating a large capacitance element of which capacitor insulation layer is made of ferroelectric layer or dielectric layer having a high dielectric constant into a semiconductor integrated circuit has been employed. In addition to this, efforts to develop a non-volatile memory operating at low voltage enabling both the high speed writing and readout by utilizing the hysteresis characteristics of ferroelectric layer have been made extensively.
A semiconductor device with a conventional built-in capacitor element is now explained by referring FIGS. 6 to 10 wherein the conventional capacitor element shown in FIG. 6 mounted on substrate 1 of semiconductor integrated circuit, consists of the first electrode 2 made of platinum selectively deposited on substrate 1, capacitor insulation layer 3 made of a dielectric layer of high dielectric constant such as a layer of Ba.sub.0.7 Sr.sub.0.3 TiO.sub.3 deposited on the first electrode 2, and second electrode 4 made of platinum deposited on capacitor insulation layer 3 avoiding its contact with the first electrode 2.
The manufacturing process of the capacitor insulation layer consists of a deposition of first electrode 2 by using a vacuum sputtering or electron-beam deposition method on the surface of substrate 1, and this is followed by a further deposition of the Ba.sub.0.7 Sr.sub.0.3 TiO.sub.3 layer on the surface by means of a spin coating, sputtering, or CVD (Chemical Vapor Deposition) method.
This is then placed in a furnace kept in an atmosphere of oxygen, and its temperature is increased to 650.degree. C. at a rate of 70.degree. C./min, and is held there for about one hour. By this, the Ba.sub.0.7 Sr.sub.0.3 TiO.sub.3 layer is sintered and the capacitor insulation layer 3 is formed.
After depositing the second electrode 4 on the surface of capacitor insulation layer 3 by means of a sputtering or electron-beam deposition method, the capacitor element is obtained by removing the unnecessary parts of first electrode 2, capacitance insulation layer 3, and the second electrode 4 by using either a plasma etching method or a wet chemical etching method.
A fine structure of the capacitor insulation layer made of Ba.sub.0.7 Sr.sub.0.3 TiO.sub.3 deposited by a conventional method and incorporated in a semiconductor device is shown in FIG. 7 by referring its cross-section wherein capacitor insulation layer 3 having a thickness of about 185 nm is constituted of number of crystal grains 5 of different grain size. The sizes of crystal grains 5 are smaller at a region closer to first electrode 2 while those are larger at a region closer to second electrode 4, and this shows that capacitor insulation layer 3 consists of number of crystal grains of different size having an average grain size of about 12 nm as shown in FIG. 8 and having a standard deviation of 3.9 nm.
FIG. 9 shows a current vs. electric field characteristics of the capacitor element with embedded capacitor insulation layer fabricated by a conventional method and is incorporated in a semiconductor device when an electric field is applied thereon, and the values of current divided by electric field are plotted on the vertical axis and the square roots of electric field are plotted on the horizontal axis.
As shown by the diagonal lines in FIG. 7, the regions where the curves determined by the respective temperatures of room-temperature, 100.degree. C., and 150.degree. C. change into linear regions are appeared at the regions where the electric field of more than 0.44 MV/cm is applied at the room temperature, 0.24 MV/cm at a temperature of 100.degree. C., and 0.07 MV/cm at 150.degree. C., and the electric field where the linear region appears is called critical electric field.
FIG. 9 shows that the carrier conduction of capacitor insulation layer of the capacitor element is governed by the Frenkel-Poole type hopping conduction when it is placed in an electric field hatched by oblique lines (For example, see Shimada et al,; The 12th Ferroelectric Material Application Conference, 26-TC-11, Kyoto, 1995).
However, a major reliability problem due to a large deviation of crystal size distribution in the capacitor insulation layer is produced when it is incorporated in a conventional semiconductor device. That is, an accelerated life test applying a DC electric field stress to the subjected capacitor element for a predetermined period under a condition of high-temperature (hereinafter this is called a high temperature bias test), and a relationship between the leak current and the test period obtained after the temperature is turned down to the room temperature within a predetermined period is determined in order to evaluate the reliability of semiconductor device with a conventional built-in capacitor element.
As a condition of the stress, a DC electric field of 0.32 MV/ca (6 V in voltage) is applied to the device kept at a temperature of 100.degree. C., and the result of this is shown in FIG. 10 wherein Curve-A shows a result of this, testing the semiconductor device with a conventional embedded capacitor element, and this shows a rapid increase in leak current of capacitor element when a testing period of more than several hundred hours is applied.
Likewise, Curve-B in FIG. 10 shows a result of the same test applied on a standard silicon semiconductor device operated at a voltage of 5 V, or for instance, a result of the accelerated test applying the same electric field and temperature between the gate electrode and the drain electrode of MOS transistor. This shows no significant change of the threshold voltage of MOS transistor even after the application of test condition of more than 1000 hours.
As shown in the above, a problem of significantly inferior reliability of semiconductor device with a conventional built-in capacitor element over that of conventional silicon semiconductor device is recognized.